Post-processing of clock trees via wiresizing and buffering for robust designPULLELA, S; MENEZES, N; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 6, pp 691-701, issn 0278-0070Article

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock netsPULLELA, S; MENEZES, N; PILEGGI, L. T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1997, Vol 16, Num 2, pp 210-215, issn 0278-0070Article

Modeling the «effective capacitance» for the RC interconnect of CMOS gatesQIAN, J; PULLELA, S; PILLAGE, L et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1994, Vol 13, Num 12, pp 1526-1535, issn 0278-0070Article

Determination of the PULSTAR reactor neutron energy spectrumPULLELA, S. V.Energy conversion and management. 1997, Vol 38, Num 10-13, pp 1015-1023, issn 0196-8904Conference Paper